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Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Features
1/3-Inch Megapixel CMOS Active-Pixel Digital Image Sensor
MT9M011
For the latest data sheet revision, please refer to Micron's Web site: www.micron.com/imaging
Features
DigitalClarity TM CMOS Imaging Technology High frame rate Superior low-light performance Low dark current Simple two-wire serial interface Auto black level calibration Operating Modes: Snapshot and flash control, high frame rate preview, electronic panning * Programmable Controls: Gain, frame size/rate, exposure, left-right and topbottom image reversal, window size, and panning * * * * * * *
Table 1:
Key Performance Parameters
Typical Value 1/3-inch (5:4) 4.6mm(H) x 3.7mm(V), 5.9mm (diagonal) 1,280H x 1,024V 3.6m x 3.6m RGB Bayer Pattern Electronic Rolling Shutter (ERS) 25 MPS/25 MHz Programmable up to 15 fps Programmable up to 60 fps Programmable up to 150 fps 10-bit, on-chip 1.0 V/lux-sec (550nm) >71dB 44dB 1.7V-3.6V 2.5V-3.1V (2.8V nominal) 2.5V-3.1V (2.8V nominal) 129mW (full resolution mode) 70mW (preview mode) -30C to +70C
Parameter Optical Format Active Imager Size Active Pixels Pixel Size Color Filter Array Shutter Type Maximum Data Rate/ Master Clock Frame SXGA (1280 x Rate 1024) VGA (640 x 480) CIF (352 x 288) ADC Resolution Responsivity Dynamic Range SNRMAX I/O Digital Supply Core Digital Voltage Analog Power Consumption Operating Temperature
Applications
* * * * Cellular phones PDAs Toys Other battery-powered products
General Description
The Micron(R) Imaging MT9M011 is an SXGA-format, 1/3-inch CMOS active-pixel digital image sensor with an active imaging pixel array of 1,280H x 1,024V. It incorporates sophisticated camera functions on-chip such as windowing, column and row skip mode, and snapshot mode. It is programmable through a simple two-wire serial interface and has low power consumption. The megapixel CMOS image sensor features DigitalClarity--Micron's breakthrough low-noise CMOS imaging technology that achieves CCD image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and integration advantages of CMOS. The sensor can be operated in its default mode or programmed by the user for frame size, exposure, gain setting, and other parameters. The default mode outputs an SXGA image at 13.9 frames per second (fps).
An on-chip analog-to-digital converter (ADC) provides 10 bits per pixel. FRAME_VALID and LINE_VALID signals are output on dedicated pins, along with a pixel clock that is synchronous with valid data. A flash output signal is also available to synchronize external light sources with sensor exposure time.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron's production data sheet specifications.
Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Table of Contents Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Pixel Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Pixel Array Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Output Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Output Data Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Serial Bus Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Bus Idle State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Start Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Stop Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Slave Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Data Bit Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 No-Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Two-wire Serial Interface Sample Write and Read Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 16-Bit Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 16-Bit Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Eight-Bit Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Eight-Bit Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Feature Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Window Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Border of Pixels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Readout Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Column Mirror Image. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Row Mirror Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Column and Row Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Digital Zoom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Frame Rate Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Readout Speeds and Power Savings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Context Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Minimum Horizontal Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Valid Data Signals Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 LINE_VALID Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 FRAME_VALID Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Integration Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Maximum Shutter Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Flash Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Recommended Gain Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Propagation Delay for FRAME_VALID and LINE_VALID Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Two-wire Serial Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Spectral Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor List of Figures List of Figures
Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Typical Configuration (Connection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pixel Array Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Pixel Color Pattern Detail (Top Right Corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Spatial Illustration of Image Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Timing Example of Pixel Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Row Timing and FRAME_VALID/LINE_VALID Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Timing Diagram Showing a Write to Reg0x09 with the Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Timing Diagram Showing a Read from Reg0x09; Returned Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . .14 Timing Diagram Showing a Write to Reg0x09 with the Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Timing Diagram Showing a Read from Reg0x09; Returned Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . .15 Readout of 6 Pixels in Normal and Column Mirror Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Readout of 6 Rows in Normal and Row Mirror Output Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Readout of 8 Pixels in Normal and Column Skip 2X Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Readout of 16 Pixels in Normal and Column Skip 4X Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Readout of 8 Pixels in Normal and Zoom 2X Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Different LINE_VALID Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 FRAME_VALID Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Xenon Flash Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 LED Flash Enabled (integration time = number of rows in a frame). . . . . . . . . . . . . . . . . . . . . . . . . . . .33 LED Flash Enabled with Restart (integration time = number of rows in a frame) . . . . . . . . . . . . . . . .33 Propagation Delays for FRAME_VALID and LINE_VALID Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Propagation Delays for PIXCLK and Data Out Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Data Output Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Serial Host Interface Start Condition Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Serial Host Interface Stop Condition Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Serial Host Interface Data Timing for Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Serial Host Interface Data Timing for Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Acknowledge Signal Timing After an 8-Bit Write to the Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Acknowledge Signal Timing After an 8-Bit Read from the Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Spectral Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor List of Tables List of Tables
Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Key Performance Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Frame Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Frame Time--Long Integration Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Register List and Default Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Reserved Register List and Default Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Recommended Gain Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor
Figure 1: Block Diagram
Control Register Active Pixel Sensor (APS) Array SXGA 1,316H x 1,048V
Serial I/O
Timing and Control
Sync Signals
Analog Processing
ADC
Data Out
Figure 2: Typical Configuration (Connection)
2.8V ANALOG 2.8V I/O 2.8V DIG ITAL
0.1F
1F +
0.1F 1F +
1F +
0.1F
DGNDQ V DDQ
DGND VAAPIX V AA V DD
AGND
1.5K
1.5K
1K
Two-Wire Serial Bus
SDATA SCLK
RESET# 10F +
DOUT9 DOUT8 DOUT7 DOUT6 DOUT5 DOUT4 DOUT3 DOUT2 DOUT1 DOUT0 PIXCLK LINE_VA LID FRAME_VALID
DGNDQ MASTER CLOCK (25 MHz) CLKIN S TA NDB Y O E# DGNDQ
FLASH
DGND
DGNDQ DGND AGND
Notes: 1. Resistor value 1.5K is recommended, but may be greater for slower two-wire speed. 2. VDD and VAA supplies must be at same potential to avoid excess current draw. Care must be taken to avoid noise injection in the analog supply is cases where a single supply is used.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
AGND
Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor
Table 2:
Signal Description
Name RESET# STANDBY OE# SCLK CLKIN SDATA LINE_VALID FRAME_VALID FLASH PIXCLK DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 DOUT8 DOUT9 VDDQ VAA VAAPIX VDD AGND DGND DGNDQ NC Type Input Input Input Input Input I/O Output Output Output Output Output Output Output Output Output Output Output Output Output Output Power Power Power Power Ground Ground Ground - Description Asynchronous reset of sensor when LOW. All registers reset to factory defaults. Enables low power standby mode when = 1. Enables output drivers when = 0. Serial Clock. Master Clock into sensor (25 MHz maximum). Serial Data. Line Valid: Active HIGH during line of selectable valid pixel data (see Reg0x20 for options). Frame Valid: Active HIGH during frame of valid pixel data. Synchronization pulse for external light source. Pixel Clock Output. Pixel data outputs are valid during rising edge of this clock. Pixel Data Output Bit 0 (LSB). Pixel Data Output Bit 1. Pixel Data Output Bit 2. Pixel Data Output Bit 3. Pixel Data Output Bit 4. Pixel Data Output Bit 5. Pixel Data Output Bit 6. Pixel Data Output Bit 7. Pixel Data Output Bit 8. Pixel Data Output Bit 9 (MSB). Digital I/O Power. Analog Power. Pixel Array Power. Digital Core Power. Analog Ground. Digital Core Ground. Digital I/O Ground. No Connect.
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Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Pixel Data Format
Pixel Data Format
Pixel Array Structure
The MT9M011 pixel array is configured as 1,316 columns by 1,048 rows (shown in Figure 3). The first 26 columns and the first eight rows of pixels are optically black, and can be used to monitor the black level. The last column and the last seven rows of pixels are also optically black. The black row data is used internally for the automatic black level adjustment. However, the first eight black rows can also be read out by setting the sensor to raw data output mode (Reg0x22). There are 1,289 columns by 1,033 rows of optically active pixels, which provides a four-pixel boundary around the SXGA (1,280 x 1,024) image to avoid boundary effects during color interpolation and correction. The additional active column and additional active row are used to allow horizontally and vertically mirrored readout to also start on the same color pixel.
Figure 3: Pixel Array Description
8 black rows (0, 0)
1 black column
SXGA (1,280 x 1,024) + 4 pixel boundary for color correction + additional active column + additional active row = 1,289 x 1,033 active pixels
26 black columns
(1315, 1047)
7 black rows
The MT9M011 uses a Bayer color pattern, shown in Figure 4. The even-numbered rows contain green and red color pixels, and odd-numbered rows contain blue and green color pixels. Even-numbered columns contain green and blue color pixels; odd-numbered columns contain red and green color pixels.
Figure 4: Pixel Color Pattern Detail (Top Right Corner)
column readout direction . . . black pixels Pixel (26, 8) G row readout direction B ... G B G B R G R G R G G B G B G B R G R G R G G B G B G B R G R G R G G B G B G B
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Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Pixel Data Format Output Data Format
The MT9M011 image data is read out in a progressive scan. Valid image data is surrounded by horizontal blanking and vertical blanking, as shown in Figure 5. The amount of horizontal blanking is programmable through Reg0x05 and Reg0x07; while vertical blanking is programmable through Reg0x06 and Reg0x08, respectively. LINE_VALID is HIGH during the shaded region of the figure. FRAME_VALID timing is described in "Output Data Timing" on page 9.
Figure 5: Spatial Illustration of Image Readout
P0,0 P0,1 P0,2.....................................P0,n-1 P0,n P1,0 P1,1 P1,2.....................................P1,n-1 P1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00
VALID IMAGE
HORIZONTAL BLANKING
Pm-1,0 Pm-1,1.....................................Pm-1,n-1 Pm-1,n 00 00 00 .................. 00 00 00 Pm,0 Pm,1.....................................Pm,n-1 Pm,n 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 VERTICAL BLANKING 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 VERTICAL/HORIZONTAL BLANKING 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00
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Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Pixel Data Format Output Data Timing
The data output of the MT9M011 is synchronized with the PIXCLK output. When LINE_VALID is HIGH, one 10-bit pixel datum is output every PIXCLK period. The PIXCLK signal is nominally the inverted of the master clock, allowing PIXCLK to be used as a clock to latch the data. It is continuously enabled, even during the blanking period. The MT9M011 can be programmed to delay the PIXCLK edge relative to the DOUT transitions from 0 to 3.5 master clocks, in steps of one-half of a master clock. This is achieved by programming the corresponding bits in Reg0x0A. The parameters P, A, and Q in Figure 7 are defined in Table 3 on page 10. The high time is defined as parameter A = (Reg0x04 x PIXCLK_PERIOD).
Figure 6: Timing Example of Pixel Data
....
LINE_VALID
....
PIXCLK
Blanking Valid Image Data
....
Blanking
DOUT9-DOUT0
P0 (9:0)
P1 (9:0)
P2 (9:0)
P3 (9:0)
P4 (9:0)
....
Pn-1 (9:0)
Pn (9:0)
Figure 7: Row Timing and FRAME_VALID/LINE_VALID Signals
...
FRAME_VALID
...
LINE_VALID
...
Number of master clocks
P
A
Q
A
Q
A
P
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Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Pixel Data Format
. Table 3:
Parameter A
Frame Time
Name Active Data Time Equation (master clocks units) Reg0x04 x PIXCLK_PERIOD (For skip 2x mode: divide Reg0x04 by 2, For skip 4x mode: divide Reg0x04 by 4) 6 x PIXCLK_PERIOD Default Timing at 25 MHZ 1,280 pixel clocks = 1,280 master = 51.2s 6 pixel clocks = 6 master = 0.24s 396 pixel clocks = 396 master = 15.84s 1,676 pixel clocks = 1,676 master = 67.04s 84,184 pixel clocks = 84,184 master = 3.37ms 1,715,840 pixel clocks = 1,715,840 master = 68.63ms 1,800,024 pixel clocks = 1,800,024 master = 72.0ms
P
Frame Start/End Blanking Horizontal Blanking
Q
HBLANK_REG x PIXCLK_PERIOD
A+Q
RowTime
(Reg0x04 + HBLANK_REG) x PIXCLK_PERIOD
V
Vertical Blanking
VBLANK_REG x (A + Q) + (Q - 2 x P)
Nrows x (A + Q)
Frame Valid Time
F
Total Frame Time
Reg0x03 x (A + Q) - (Q - 2 x P) (For skip 2x mode: divide Reg0x03 by 2, For skip 4x mode: divide Reg0x03 by 4) (Reg0x03 + VBLANK_REG) x (A + Q)
1ADC_MODE: Reg0xC8, bit 3 = 1: Reg0x20, bit 10 Reg0xC8, bit 3 = 0: Reg0x21, bit 10 (0 = 2 ADC mode, 1 = 1 ADC mode) Default = 0 HBLANK_REG: Reg0xC8, bit 0 = 1: Reg0x05 Reg0xC8, bit 0 = 0: Reg0x07 1ADC_MODE = 0: Minimum value is 202, 1ADC_MODE = 1: Minimum value is 114 Default = 396 (13.9 fps) Note: For frame rate of 15 fps, set Reg0x05 to 272
VBLANK_REG: Reg0xC8, bit 1 = 1: Reg0x06 Reg0xC8, bit 1 = 0: Reg0x08 Minimum value: sum of dark and extra rows enabled in Reg0x22 and Reg0x24 Default = 50 PIXCLK_PERIOD: 1ADC_MODE = 0: Reg0x0A, bit 3 - 0 1ADC_MODE = 1: (Reg0x0A, bit 3 - 0) x 2 A value of 0 in the register is not allowed. Default = 1
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Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Pixel Data Format
The sensor timing is shown in terms of pixel clock and master clock cycles (please refer to Figure 6 on page 9). The recommended master clock frequency is 25 MHz. The vertical blank and total frame time equations assume that the number of integration rows (Reg0x09) is less than or equal to the number of active rows plus blanking rows (Reg0x03 + VBLANK_REG). If this is not the case, the number of integration rows must be used instead to determine the frame time, as shown in Table 4.
Table 4:
Parameter V' F'
Frame Time--Long Integration Time
Name Vertical Blanking (long integration time) Total Frame Time (long integration time) Equation (master clock) (Reg0x09 - Reg0x03) x (A + Q) + (Q - 2 x P) (Reg0x09) x (A + Q) Default Timing 84,184 pixel clocks = 3.37ms 1,800,024 pixel clocks = 72.0ms
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Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Serial Bus Description
Serial Bus Description
Registers are written to and read from the MT9M011 through the two-wire serial interface bus. The sensor is a serial interface slave and is controlled by the serial clock (SCLK), which is driven by the serial interface master. Data is transferred into and out of the MT9M011 through the serial data (SDATA) line. The SDATA line is pulled up to 2.8V offchip by a 1.5K resistor. Either the slave or master device can pull the SDATA line down-- the serial interface protocol determines which device is allowed to pull the SDATA line down at any given time.
Protocol
The two-wire serial interface defines several different transmission codes, as follows: * * * * * a start bit the slave device 8-bit address a(an) (no) acknowledge bit an 8-bit message a stop bit
Sequence
A typical read or write sequence begins by the master sending a start bit. After the start bit, the master sends the slave device's 8-bit address. The last bit of the address determines if the request will be a read or a write, where a "0" indicates a write and a "1" indicates a read. The slave device acknowledges its address by sending an acknowledge bit back to the master. If the request was a write, the master then transfers the 8-bit register address to which a write should take place. The slave sends an acknowledge bit to indicate that the register address has been received. The master then transfers the data 8 bits at a time, with the slave sending an acknowledge bit after each 8 bits. The MT9M011 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers to write to one register. After 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register address. The master stops writing by sending a start or stop bit. A typical read sequence is executed as follows. First the master sends the write-mode slave address and 8-bit register address, just as in the write request. The master then sends a start bit and the read-mode slave address. The master then clocks out the register data 8 bits at a time. The master sends an acknowledge bit after each 8-bit transfer. The register address is auto-incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a no-acknowledge bit.
Bus Idle State
The bus is idle when both the data and clock lines are HIGH. Control of the bus is initiated with a start bit, and the bus is released with a stop bit. Only the master can generate the start and stop bits.
Start Bit
The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line is HIGH.
Stop Bit
The stop bit is defined as a LOW-to-HIGH transition of the data line while the clock line is HIGH.
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Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Serial Bus Description Slave Address
The 8-bit address of a two-wire serial interface device consists of 7 bits of address and 1 bit of direction. A "0" (0xBA) in the LSB (least significant bit) of the address indicates write mode, and a "1" (0xBB) indicates read mode.
Data Bit Transfer
One data bit is transferred during each clock pulse. The serial interface clock pulse is provided by the master. The data must be stable during the HIGH period of the two-wire serial interface clock--it can only change when the serial clock is LOW. Data is transferred 8 bits at a time, followed by an acknowledge bit.
Acknowledge Bit
The master generates the acknowledge clock pulse. The transmitter (which is the master when writing, or the slave when reading) releases the data line, and the receiver indicates an acknowledge bit by pulling the data line LOW during the acknowledge clock pulse.
No-Acknowledge Bit
The no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate a read sequence.
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Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Two-wire Serial Interface Sample Write and Read Sequences
Two-wire Serial Interface Sample Write and Read Sequences
16-Bit Write Sequence
A typical write sequence for writing 16 bits to a register is shown in Figure 8. A start bit given by the master, followed by the write address, starts the sequence. The image sensor will then give an acknowledge bit and expects the register address to come first, followed by the 16-bit data. After each 8-bit transfer, the image sensor will give an acknowledge bit. All 16 bits must be written before the register will be updated. After 16 bits are transferred, the register address is automatically incremented so that the next 16 bits are written to the next register. The master stops writing by sending a start or stop bit.
Figure 8: Timing Diagram Showing a Write to Reg0x09 with the Value 0x0284
SCLK
SDATA 0xBA ADDR START ACK Reg0x09 ACK 0000 0010 ACK 1000 0100 ACK
STOP
16-Bit Read Sequence
A typical read sequence is shown in Figure 9. First the master has to write the register address, as in a write sequence. Then a start bit and the read address specifies that a read is about to happen from the register. The master then clocks out the register data 8 bits at a time. The master sends an acknowledge bit after each 8-bit transfer. The register address should be incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a no-acknowledge bit.
Figure 9: Timing Diagram Showing a Read from Reg0x09; Returned Value 0x0284
SCLK
SDATA 0xBA ADDR START ACK Reg0x09 ACK 0xBB ADDR ACK 0000 0010 ACK 1000 0100 NACK
STOP
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Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Two-wire Serial Interface Sample Write and Read Sequences Eight-Bit Write Sequence
To be able to write one byte at a time to the register a special register address is added. The 8-bit write is done by first writing the upper 8 bits to the desired register and then writing the lower 8 bits to the special register address (Reg0xF1). The register is not updated until all 16 bits have been written. It is not possible to just update half of a register. In Figure 10 a typical sequence for 8-bit writing is shown. The second byte is written to the special register (Reg0xF1).
Figure 10: Timing Diagram Showing a Write to Reg0x09 with the Value 0x0284
SCLK SDATA
0xBA ADDR
Reg0x09
0000 0010
0xBA ADDR
Reg0xF1
1000 0100 STOP
START START ACK ACK ACK ACK ACK ACK
Eight-Bit Read Sequence
To read one byte at a time the same special register address is used for the lower byte. The upper 8 bits are read from the desired register. By following this with a read from the special register (Reg0xF1) the lower 8 bits are accessed (Figure 11). The master sets the no-acknowledge bits.
Figure 11: Timing Diagram Showing a Read from Reg0x09; Returned Value 0x0284
SCLK SDATA
0xBA ADDR
Reg0x09 START
0xBB ADDR
0000 0010
START
ACK
ACK
ACK
NACK
SCLK SDATA
0xBA ADDR
Reg0xF1 START
0xBB ADDR
1000 0100 STOP ACK NACK
START
ACK
ACK
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Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Registers
Registers
Table 5: Register List and Default Value
Register Number (Hex) 0x00/0xFF 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x1F 0x20 0x21 0x22 0x23 0x2B 0x2C 0x2D 0x2E 0x2F 0xC8 Note: Description Chip Version Row Start Column Start Row Width Column Width Horizontal Blanking B Vertical Blanking B Horizontal Blanking A Vertical Blanking A Shutter Width Row Speed Extra Delay Shutter Delay Reset Frame Valid Control Read Mode B Read Mode A Dark Col/Rows Flash Green1 Gain Blue Gain Red Gain Green2 Gain Global Gain Context Control Data Format (Binary) 0001 0100 0010 0010 (LSB) 0000 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd 00dd dddd dddd dddd 0ddd dddd dddd dddd 00dd dddd dddd dddd 0ddd dddd dddd dddd dddd dddd dddd dddd ddd0 000d dddd dddd 00dd dddd dddd dddd 00dd dddd dddd dddd d000 00dd 00dd dddd dddd dddd dddd dddd dd00 0ddd dddd dddd 0000 0d00 0000 dd00 0000 00dd dddd dddd ??dd dddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd 0000 0ddd dddd dddd d000 0000 d000 dddd Default Value (Hex) 0x1433 0x000C 0x001E 0x0400 0x0500 0x018C 0x0032 0x00C6 0x0019 0x0432 0x0011 0x0000 0x0000 0x0008 0x0000 0x0200 0x040C 0x0129 0x0608 0x0020 0x0020 0x0020 0x0020 0x0020 0x000B
1 = always 1 0 = always 0 d = programmable ? = read only
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Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Registers Table 6: Reserved Register List and Default Value
Register Number (Hex) 0x24 0x30 0x31 0x32 0x33 0x34 0x36 0x37 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 0x61 0x62 0x63 0x64 0x65 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x80 Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default Value (Hex) 0x806F 0x042A 0x1C00 0x0000 0x0349 0xC019 0xF0F0 0x0000 0x0021 0x1A20 0x201E 0x2020 0x2020 0x201C 0x00D7 0x0777 0x000C 0xC00F RO RO RO RO 0x231D 0x0080 0x0000 0x0000 0x0000 0x0000 0x0000 0x7B0A 0x7B0A 0x190E 0x180F 0x5732 0x5634 0x7335 0x3012 0x7902 0x7506 0x770A 0x7809 0x7D06 0x3110 0x007E 0x007F
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Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Registers Table 6: Reserved Register List and Default Value
Register Number (Hex) 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0xF0 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD Note: Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default Value (Hex) 0x007F 0x570A 0x580B 0x470B 0x480E 0x5B02 0x005C 0x0000 0x07FF 0x07FF 0x0000 0x0000 0x007C 0x0000 0x0000 0x0000 0x0000
Writing to these registers may cause the part to go into an unknown state.
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Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Registers Table 7: Register Description
Default (Hex) 1433 0C Y YM Sync'd to Frame Start Bad Frame Read/ write R W
Bit
Bit Description
0x00/0xFF (0/255) Chip Version 15:0 Chip Version Chip version - read-only. 0x01 (1) Row Start 10:0 Row Start The first row to be read out (not counting any dark rows that may be read). To window the image down, set this register to the starting Y value. Setting a value less than 8 is not recommended since the dark rows should be read using Reg0x22. 0x02 (2) Column Start 10:0 Column Start The first column to be read out (not counting dark columns that may be read). To window the image down, set this register to the starting X value. Setting a value below 24 decimals (0x18) is not recommended since readout of dark columns should be controlled by Reg0x22. 0x03 (3) Row Width 10:0 Row Width Number of rows in the image to be read out (not counting any dark rows or border rows that may be read). 0x04 (4) Column Width 10:0 Column Width Number of columns in image to be read out (not counting any dark columns or border columns that may be read). 0x05 (5) Horizontal Blanking B 10:0 Horizontal Number of blank columns in a row when context B is Blanking B chosen (Reg0xC8, bit 0 = 1). If set smaller than the minimum value the minimum value will be used. With default settings the minimum horizontal blanking will be 202 columns when using two ADCs and 114 columns when using one ADC. Default of 0x18C = 13.9 fps @ 25 MHz Setting of 0x110 = 15 fps @ 25 MHz 0x06 (6) Vertical Blanking B 14:0 Vertical Number of blank rows in a frame when context B is Blanking B chosen (Reg0xC8, bit 1 = 1). This number must be equal to or larger than the number of dark rows read out in a frame specified by Reg0x22. 0x07 (7) Horizontal Blanking A 10:0 Horizontal Number of blank columns in a row when context A is Blanking A chosen (Reg0xC8, bit 0 = 0). The extra columns will be added at the beginning of a row. If set smaller than the minimum value the minimum value will be used. With default settings the minimum horizontal blanking will be 202 columns when using two ADCs and 114 columns when using one ADC. Default of 0xC6 = 27.8 fps @ 25 MHz Setting of 0x88 = 30 fps @ 25 MHz
1E
Y
YM
W
400
Y
YM
W
500
Y
YM
W
18C
Y
YM
W
32
Y
N
W
C6
Y
YM
W
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Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Registers Table 7: Register Description (Continued)
Default (Hex) 19 Sync'd to Frame Start Y Bad Frame N Read/ write W
Bit
Bit Description
0x08 (8) Vertical Blanking A 14:0 Vertical Number of blank rows in a frame when context A is Blanking A chosen (Reg0xC8, bit 1 = 1). This number must be equal to or larger than the number of dark rows read out in a frame specified by Reg0x22. 0x09 (9) Shutter Width 15:0 Shutter Width Integration time in number of rows. In addition to this register the shutter delay register (Reg0x0C) and the overhead time will influence the integration time for a given row time. 0x0A (10) Row Speed 3:0 Pixel Clock Pixel clock period in master clocks when two ADCs are Period used (Reg0x20/0x21, bit 10 = 0). The ADC clock will always be half the programmed frequency. When only one ADC is used the pixel clock frequency will be halved as well, so in this case will be equal to the ADC clock frequency. The value "0" is not allowed, "1" will be used instead. 7:4 Delay Pixel Delay PIXCLK in half master clock cycles. When set the Clock pixel clock can be delayed in increments of half master clock cycles compared to the synchronization of FRAME_VALID, LINE_VALID and DATA_OUT. 8 Invert Pixel Invert pixel clock. When set, LINE_VALID, FRAME Clock _VALID, and DATA_OUT will be set up to the falling edge of PIXCLK. When clear, they are set up to the rising edge if there are no delay of the pixel clock. 15:14 Reserved - 0x0B (11) Extra Delay 13:0 Extra Delay Extra blanking inserted between frames specified in pixel clocks. Can be used to get a more exact frame rate. It might affect the integration times of parts of the image when the integration time is less than one frame. 0x0C (12) Shutter Delay 10:0 Shutter Delay The amount of time from the end of the sampling sequence to the beginning of the pixel reset sequence. This variable will automatically be halved when one ADC is used so the time in us will remain the same. This register has an upper value defined by the fact that the reset needs to finish before the readout of that row to prevent changes in the row time.
432
Y
N
W
1
Y
YM
W
1
N
W
0
N
W
0 0
- Y
-
- W
0
Y
N
W
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Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Registers Table 7: Register Description (Continued)
Default (Hex) 0 Sync'd to Frame Start N Bad Frame YM Read/ write W
Bit 0x0D (13) Reset 0 Reset
Bit Description
Setting this bit will put the sensor into reset mode, which will set the sensor to its default power-up state. Clearing this bit will resume normal operation. 1 Restart Setting this bit will cause the sensor to abandon the current frame and start resetting the first row. The delay before the first valid frame is read out equals the integration time. This bit always reads "0." 2 Analog standby 0 = normal operation (default). 1 = disable analog circuitry. 3 Chip Enable 1 = normal operation. 0 = stop sensor readout. When this is returned to "1," sensor readout restarts and starts resetting the starting row in a new frame. To reduce the digital power further the master clock to the sensor can be disabled or the standby pin can be used. 4 - Reserved 5 - Reserved 8 Show bad 1 = output all frames (including bad frames). frames 0 = only output good frames (default). A bad frame is defined as the first frame following a change to: window size or position, horizontal blanking, pixel clock speed, zoom, row or column skip, or mirroring. 9 Restart bad When set a restart will be forced to take place when a frames bad frame is detected. This can shorten the delay when waiting for a good frame, since the delay when masking out a bad frame will be the integration time rather than the full frame time. 15 Synchronize 0 = normal operation, update changes to registers that changes affect image brightness (integration time, integration delay, gain, horizontal and vertical blanking, window size, row/column skip, or row mirror) at the next frame boundary. 1 = do not update any changes to these settings until this bit is returned to "0." All registers that are frame synchronized will be affected by the setting of this bit. 0x1F (31) FRAME_VALID Control 6:0 Early When enabled, the FRAME_VALID rising edge will FRAME_VALID happen for the programmed number of rows before rise the first LINE_VALID: (bits 6:0) x row time + horiz blank + constant (constant = 3 in default mode). 7 Enable early 1 = Enables the early rise of FRAME_VALID as set in bits FRAME_VALID 6:0. rise 0 = default. FRAME_VALID will go HIGH six pixel clocks before first LINE_VALID.
0
N
YM
W
0 1
N N
YM YM
W W
0 0 0
- - N
- -
- - W
0
N
W
0
N
W
0
N
W
0
N
W
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Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Registers Table 7: Register Description (Continued)
Default (Hex) 0 Sync'd to Frame Start N Bad Frame Read/ write W
Bit 14:8 Early FRAME_VALID fall
Bit Description When enabled the FRAME_VALID falling edge will happen the programmed number of rows before the end of the last LINE_VALID: (1 + bits 14:8) x row time + constant (constant = 3 in default mode). 1 = Enables the early disabling of FRAME_VALID as set in bits 14:8. Note that LINE_VALID will still be generated for all active rows. 0 = default. FRAME_VALID will go LOW six pixel clocks after last LINE_VALID. - Context B Read out rows from bottom to top (upside down). When set, row readout starts from row (Row Start + Row Size) and continues down to (Row Start + 1). When clear, readout starts at Row Start and continues to (Row Start + Row Size - 1). This ensures that the starting color is maintained. Read out columns from right to left (mirrored). When set, column readout starts from column (Col Start + Col Size) and continues down to (Col Start + 1). When clear, readout starts at Col Start and continues to (Col Start + Col Size - 1). This ensures that the starting color is maintained. When Read Mode context B is selected (Reg0xC8, bit 3 = 1): 1 = read out two rows, and then skip two rows (i.e. row 8, row 9, row 12, row 13...). 0 = normal readout. When Read Mode context B is selected (Reg0xC8, bit 3 = 1): 1 = read out two columns, and then skip two columns (as with rows). 0 = normal readout. 1 = read out two rows, and then skip six rows (i.e. row 8, row 9, row 16, row 17...). 0 = normal readout. 1 = read out two columns, and then skip six columns (as with rows). 0 = normal readout.
15
Enable early FRAME_VALID fall
0
N
W
0x20 (32) Read Mode 0 Mirror rows
0
Y
YM
W
1
Mirror columns
0
Y
YM
W
2
Row skip 2x context B
0
Y
YM
W
3
Column skip 2x - context B
0
Y
YM
W
4
Row skip 4x
0
Y
YM
W
5
Column skip 4x
0
Y
YM
W
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Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Registers Table 7: Register Description (Continued)
Default (Hex) 0 Sync'd to Frame Start Y Bad Frame YM Read/ write W
Bit 7:6 Zoom
Bit Description In zoom mode, the pixel data rate is slowed down by a factor of either 2 or 4, and either 1 or 3 additional blank rows are added between each output row. This is designed to give the controller logic time to repeat data to fill in a window that is either 2 or 4 times larger with repeated data. The pixel clock speed is not affected by this operation, and the output data for each pixel is valid for either 2 or 4 pixel clocks. In 2X zoom mode, every row is followed by a blank row (with its own LINE_VALID, but all data bits = 0) of equal time. In 4X zoom mode, every row is followed by three blank rows. The combination of this register and an appropriate change to the window start registers allows the user to zoom to a region of interest without affecting the frame rate. 00 = no zoom (default) X1 = zoom 2X 10 = zoom 4X When this bit is set a 4-pixel border will be output around the active image array independent of readout mode (skip, zoom, mirror, etc.). Setting this bit will therefore add eight to the number of rows and columns in the frame. This bit indicates whether to show the border enabled by bit 8. When bit 8 is 0 this bit has no meaning. When bit 8 is 1, this bit decides whether the border pixels should be treated as extra active pixels (1) or extra blanking pixels (0). 0 = Use both ADCs to achieve maximum speed. 1 = Use one ADC to reduce power. Maximum readout frequency is now half of the master clock, and the pixel clock is automatically adjusted as described for the pixel clock speed register. 1 = "Continuous" Line_Valid (continue producing line valid during vertical blanking). 0 = Normal Line_Valid (default) no line valid during vertical blanking. 1 = Line valid = "Continuous" Line_Valid XOR Frame Valid. 0 = Normal Line Valid. Ineffective if Continuous Line_Valid is set.
8
Over Sized
0
Y
YM
W
9
Show Border
1
N
W
10
Use 1 ADC Context B
0
Y
YM
W
14
Continuous Line Valid
0
N
W
15
Xor Line Valid
0
N
W
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Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Registers Table 7: Register Description (Continued)
Default (Hex) 1 Sync'd to Frame Start Y Bad Frame YM Read/ write W
Bit
Bit Description
0x21 (33) Read Mode - Context A 2 Row skip 2x When Read Mode context A is selected (Reg0xC8, bit 3 Context A = 0): 1 = read out two rows, and then skip two rows (i.e. row 8, row 9, row 12, row 13...). 0 = normal readout. 3 Column skip 2x When Read Mode context A is selected (Reg0xC8, bit 3 - Context A = 0): 1 = read out two columns, and then skip two columns (as with rows). 0 = normal readout. 10 1 ADC mode When Read Mode context A is selected (Reg0xC8, bit 3 Context A = 0): 0 = Use both ADCs to achieve maximum speed. 1 = Use one ADC to reduce power. Maximum readout frequency is now half of the master clock, and the pixel clock is automatically adjusted as described for the pixel clock speed register. 0x22 (34) Show Control 2:0 Number of dark Specifies the number of dark rows to read out at the rows beginning of each frame when the dark row readout is enabled (bit 3). The programmed number is 1 less than the number of rows. 3 Enable dark Enables the readout of the dark rows specified in bits row readout 2:0. 6:4 Dark start The start address for the dark rows. Must be set so all address dark rows read out falls in the address space 0-7. 7 Show dark rows When set, the programmed dark rows will be output before the active window. Frame valid will thus be asserted earlier than normal. This has no effect on integration time or frame rate. Whether the dark rows are shown in the image or not the definition frame start is before the dark rows are read out. All frame synced registers will be updated at this point. 8 Read dark When disabled, an arbitrary number of dark columns columns can be read out by including them in the active image. Enabling the dark columns do not have an effect on the row time, but it will increase the minimum horizontal blanking value allowed. 9 Show dark When set, the programmed dark columns will be columns output before the active pixels in a line. 0x23 (35) Flash Control 7:0 Xenon count Length of FLASH_STROBE pulse when Xenon flash is enabled. The value specifies the length in 1,024 master clock cycle increments. 8 LED flash Enable LED flash. When set, the FLASH_STROBE will go on prior to the start of the resetting of a frame. When disabled the FLASH_STROBE will remain high until the finish of the readout of the current frame.
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1
Y
YM
W
1
Y
YM
W
1
N
Y
W
1 2 0
N N N
Y N N
W W W
1
N
Y
W
0
N
N
W
8
N
N
W
0
Y
Y
W
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Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Registers Table 7: Register Description (Continued)
Default (Hex) 1 1 Sync'd to Frame Start N N Bad Frame N N Read/ write W W
Bit 9 Every frame
Bit Description
1 = Flash should be enabled every frame. 0 = Flash should be enabled for 1 frame only. 10 End of reset 1 = In Xenon mode the flash should be triggered after the resetting of a frame. 0 = In Xenon mode the flash should be enabled after the readout of a frame. 12:11 Frame delay Delay of the flash pulse measured in frames. 13 Xenon flash Enable Xenon flash. When set, the output pin FLASH_STROBE will be pulsed high for the programmed period during vertical blanking. This is achieved by keeping the integration time equal to one frame, and the pulse width less than the vertical blanking time. 14 Reserved - 15 FLASH_STROBE Read-only bit that indicated whether the FLASH_STROBE pin is enabled. 0x2B (43) Green1 Gain 6:0 Initial gain Initial Gain = bits (6:0) x 0.03125. 8:7 Analog gain Analog Gain = (Bit 8 + 1) x (Bit 7 + 1) x initial gain (each bit gives 2x Gain). 10:9 Digital gain Total Gain = (Bit 9 + 1) x (Bit 10 + 1) x analog gain (each bit gives 2x gain). 0x2C (44) Blue Gain 6:0 Initial gain Initial Gain = bits (6:0) x 0.03125. 8:7 Analog gain Analog Gain = (Bit 8 + 1) x (Bit 7 + 1) x initial gain (each bit gives 2x gain). 10:9 Digital gain Total Gain = (Bit 9 + 1) x (Bit 10 + 1) x analog gain (each bit gives 2x gain). 0x2D (45) Red Gain 6:0 Initial gain Initial Gain = bits (6:0) x 0.03125. 8:7 Analog gain Analog Gain = (Bit 8 + 1) x (Bit 7 + 1) x initial gain (each bit gives 2x gain). 10:9 Digital gain Total Gain = (Bit 9 + 1) x (Bit 10 + 1) x analog gain (each bit gives 2x gain). 0x2E (46) Green2 Gain 6:0 Initial gain Initial Gain = bits (6:0) x 0.03125. 8:7 Analog gain Analog Gain = (Bit 8 + 1) x (Bit 7 + 1) x initial gain (each bit gives 2x gain). 10:9 Digital gain Total Gain = (Bit 9 + 1) x (Bit 10 + 1) x analog gain (each bit gives 2x gain). 0x2F (47) Global Gain 10:0 Global Gain This register can be used to set all four gains at once. When read, it will return the value stored in Reg0x2B.
0 0
N Y
N N
W W
0 0
-
-
- W
20 0 0
Y Y Y
N N N
W W W
20 0 0
Y Y Y
N N N
W W W
20 0 0
Y Y Y
N N N
W W W
20 0 0
Y Y Y
N N N
W W W
20
Y
N
W
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Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Registers Table 7: Register Description (Continued)
Default (Hex) 1 1 0 1 Sync'd to Frame Start Y Y Y Y Bad Frame YM YM Y YM Read/ write W W W W
Bit
Bit Description
0xC8 (200) Context Control 0 Horizontal 1 = Use Horizontal Blanking context B, Reg0x05. blanking select 0 = Use Horizontal Blanking context A, Reg0x07. 1 Vertical 1 = Use Vertical Blanking context B, Reg0x06. blanking select 0 = Use Vertical Blanking context A, Reg0x08. 2 LED flash Enable LED flash. Same physical register as Reg0x23, bit enable 8. 3 Read mode 1 = Use Read Mode context B, Reg0x20. select 0 = Use Read Mode context A, Reg0x21. Note that bits only found in Read Mode context B register will always be taken from this register. 7 Xenon flash Enable Xenon flash. Same physical register as Reg0x23, enable bit 13. 15 Restart Setting this bit will cause the sensor to abandon the current frame and start resetting the first row. Same physical register as Reg0x0D, bit 1. The following notation is used in Table 7:
0 0
Y N
N YM
W W
Sync'd to frame start N = No. The register value will be updated and used immediately. Y = Yes. The register value will be updated at next frame start as long as the synchronize changes bit is 0. Note also that frame start is defined as when the first dark row is read out. By default this is eight rows before FRAME_VALID goes HIGH Bad frame A bad frame is a frame where all rows do not have the same integration time, or offsets to the pixel values changed during the frame. N = No. Changing the register value will not produce a bad frame. Y = Yes. Changing the register value might produce a bad frame. YM = Yes, but the bad frame will be masked out unless the show bad frames feature is enabled. Read/Write R = Read-only register/bit. W = Read/Write register/bit.
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Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Feature Description
Feature Description
Window Control
Reg0x01 Row Start, Reg0x02 Column Start, Reg0x03 Row Width, and Reg0x04 Column Width These registers control the size and starting coordinates of the window. By changing these registers, any image format smaller than or equal to SXGA can be specified.
Border of Pixels
Reg0x20, bits 8 and 9 By setting these register bits, a four-pixel border will be added around the specified image. Since the border is independent of the readout mode, this border can then be used as extra pixels for image processing algorithms. This means that even in the skip modes, a four-pixel border will be output in the image. When enabled, eight rows and columns must be added to the settings in the row and column width to get the new window size. If the border is enabled but not shown in the image (bits 9-8 = 01), eight rows and columns should be added to the horizontal and vertical blanking numbers instead.
Readout Modes
Column Mirror Image By setting bit 1 of Reg0x20, the readout order of the columns will be reversed as shown in Figure 12. The starting color will be preserved when mirroring the columns. Row Mirror Image By setting bit 0 of Reg0x20, the readout order of the rows will be reversed as shown in Figure 13. The starting color will be preserved when mirroring the rows.
Figure 12: Readout of 6 Pixels in Normal and Column Mirror Output Mode
LINE_VALID Normal readout DOUT9-DOUT0
G0 (9:0) R0 (9:0) G1 (9:0) R1 (9:0) G2 (9:0) R2 (9:0)
Reverse readout DOUT9-DOUT0
G3 (9:0)
R2 (9:0)
G2 (9:0)
R1 (9:0)
G1 (9:0)
R0 (9:0)
Figure 13: Readout of 6 Rows in Normal and Row Mirror Output Mode
FRAME_VALID Normal readout DOUT9-DOUT0 Reverse readout DOUT9-DOUT0 Row6 (9:0) Row5 (9:0) Row4 (9:0) Row3 (9:0) Row2 (9:0) Row1 (9:0) Row0 (9:0) Row1 (9:0) Row2 (9:0) Row3 (9:0) Row4 (9:0) Row5 (9:0)
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Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Feature Description
Column and Row Skip By setting bit 3 of Reg0x20 (Reg0x21), only half of the columns set will be read out, as shown in Figure 14. To preserve the Bayer pattern in the pixel array pair of columns are read out or skipped. The row skip mode works in the same way, and will read out two rows and then sip two. The row skip works in the same way and will only read out rows with bit 1 equal to "0." Row skip mode is enabled by setting bit 2 of Reg0x20. For both row and column skips, the number of rows or columns read out will be half of what is set in Reg0x03 or Reg0x04, respectively. The sensor can also be programmed to only read out a sixteenth of the specified window size by setting bits 4 and 5 of Reg0x20, as shown in Figure 15 (Bayer pattern is preserved).
Figure 14: Readout of 8 Pixels in Normal and Column Skip 2X Output Mode
LINE_VALID Normal readout DOUT9-DOUT0 G0 (9:0) R0 (9:0) G1 (9:0) R1 (9:0) G2 (9:0) R2 (9:0) G3 (9:0) R3 (9:0)
LINE_VALID Column skip readout DOUT9-DOUT0 G0 (9:0) R0 (9:0) G2 (9:0) R2 (9:0)
Figure 15: Readout of 16 Pixels in Normal and Column Skip 4X Output Mode
LINE_VALID Normal readout DOUT9-DOUT0 G0 (9:0) R0 (9:0) G1 (9:0) R1 (9:0) G2 (9:0) .... G7 (9:0) R7 (9:0)
LINE_VALID Column skip readout DOUT9-DOUT0 G0 (9:0) R0 (9:0) G4 (9:0) R4 (9:0)
Digital Zoom Reg0x20, bits 7:6 Digital Zoom In zoom mode, the pixel data rate is slowed down by a factor of either 2 or 4, and either 1 or 3 additional blank rows are added between each output row. This is designed to give the controller logic time to repeat data to fill in a window that is either 4 or 16 times larger with repeated data. The pixel clock speed is not affected by this operation, and the output data for each pixel is valid for either 2 or 4 pixel clocks. In 2X zoom mode, every row is followed by a blank row (with its own line valid, but all data bits = 0) of equal time. In 4X zoom mode, every row is followed by three blank rows. In the zoom modes, Reg0x03 and Reg0x04 will still specify the window size out of the sensor including the extra blanking, so the active image read out will in effect be a quarter or a sixteenth of the output image.
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Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Feature Description Figure 16: Readout of 8 Pixels in Normal and Zoom 2X Output Mode
LINE_VALID Normal readout DOUT9-DOUT0 PIXCLK
G0 (9:0) R0 (9:0) G1 (9:0) R1 (9:0) G2 (9:0) R2 (9:0) G3 (9:0) R3 (9:0)
LINE_VALID Zoom 2X readout DOUT9-DOUT0 PIXCLK
G0 (9:0) R0 (9:0) G1 (9:0) R1 (9:0)
Frame Rate Control When a window size is set, the blanking registers (Reg0x05-Reg0x08) along with the Row Speed Register (Reg0x0A) will let you program a desired frame rate. The frame timing equations at the beginning of this document shows you how to calculate the different timings. If these equations are turned around they can help you set the horizontal or vertical blanking values to achieve a desired frame rate: HBLANK_REG = master clock freq / (frame rate x (Reg0x03 + VBLANK_REG) x PIXCLK_PERIOD) - Reg0x04 VBLANK_REG = master clock freq / (frame rate x (Reg0x04 + HBLANK_REG) x PIXCLK_PERIOD) - Reg0x03 Readout Speeds and Power Savings The MT9M011 sensor has two ADCs to convert the pixel values to digital. Since the ADCs run at half the master clock frequency, this makes it possible to achieve a data rate equal to the master clock frequency. On the other hand, it also makes it an option for slower readout to turn one of the ADCs off in order to reduce the power consumption of the sensor. Reg0x20 (Reg0x21), bit 10, chooses between the two modes: 0 = Use both ADCs and read out at the set pixel clock frequency (Reg0x0A, bits 3:0) 1 = Use 1 ADC and read out at half the set pixel clock frequency (Reg0x0A, bits 3:0) This can be used, for example, when the camera is in preview mode. To make the transitions between two sensor settings easier, some simple context switching is available in the MT9M011, as described below. Context Switching Reg0xC8 is designed to help switching between sensor modes easily. Some key registers and bits in the sensor have two physical register locations, called contexts. Bits 0, 1, and 3 of Reg0xC8 will decide which context of the register that is currently in use. A 1 in a bit will choose context B, while a 0 will select context A for that parameter. The select bits can be used in any combination, but by default it is set up to make switching between a preview mode to a full resolution mode easy: Full resolution mode: (default) Context B: Reg0xC8 = 0x000B (Context B) Reg0x05 = 0x018C (Horizontal Blanking) Reg0x06 = 0x0032 (Vertical Blanking) Reg0x20, bit 10 = 0, bit 3 = 0, bit 2 = 0 (2 ADCs, no column or row skip) A full resolution SXGA picture will be output at the master clock frequency at 13.9 fps.
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Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Feature Description
Context A: Reg0xC8 = 0x0000 (Context A) Reg0x07 = 0x00C6 (Horizontal Blanking) Reg0x08 = 0x0019 (Vertical Blanking) Reg0x21, bit 10 = 1, bit 3 = 1, bit 2 = 1 (1 ADC, column and row skip enabled) A preview image (half SXGA size) will be output at half of the master clock frequency at 27.8 fps. Note that the horizontal and vertical blanking values are set so the row time will be preserved in the two modes. This way, a switch between the modes will not affect the integration time. This is also the reason that the shutter delay register (Reg0x0C) is automatically halved in 1 ADC mode. A few more control bits are also available through the context register (Reg0xC8) so flash and restarting of the sensor can be done at the same time as changing the contexts. See Table 7, Register Description, on page 19 for more information. Minimum Horizontal Blanking The minimum horizontal blanking value is constrained by the time used for sampling a row of pixels and the overhead in the readout of a row. This can be expressed in an equation as: min hblank = sampling time + dark col time + overhead 2 ADC Mode: min hblank = 20 x (Reg0x22, bit 8) + 182 = 202 (default) 1 ADC Mode: min hblank = 20 x (Reg0x22, bit 8) + 94 = 114 (default)
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Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Feature Description Valid Data Signals Options
LINE_VALID Signal By setting Bit 9 and 10 of Reg0x20, the LINE_VALID signal can be programmed for three different output formats. The formats shown below illustrate reading out four rows and two vertical blanking rows (Figure 17). In the last format, the LINE_VALID signal is the XOR between the continuous LINE_VALID signal and the FRAME_VALID signal.
Figure 17: Different LINE_VALID Formats
Default FRAME_VALID LINE_VALID Continuously FRAME_VALID LINE_VALID XOR FRAME_VALID LINE_VALID
FRAME_VALID Signal Each edge of the FRAME_VALID signal can be programmed to occur earlier than the default time described in the frame timing equations. This is useful if a controller chip needs advanced notice that an image is ready and will be read out. Reg0x1F is used for this flexibility; Table 7, Register Description, on page 19 provides more information and equations concerning the time when the FRAME_VALID action will take place.
Figure 18: FRAME_VALID Signals
LINE_VALID FRAME_VALID Reg0x1F = 0x0000 FRAME_VALID Reg0x1F = 0x8080 FRAME_VALID Reg0x1F = 0x8181
Note:
The stippled LINE_VALID pulses are for illustration purposes only. The rising and falling edges can be programmed independently.
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Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Feature Description Integration Time
The following registers along with the row time control the integration time: Register 0x09: Register 0x0C: number of rows of integration, default = 0x0432 (1074) shutter delay, default = 0x0000 (0). This is the number of pixel clocks that the timing and control logic waits before asserting the reset for a given row The actual total integration time, tINT, is:
tINT
= Reg0x09 x Row Time - Overhead Time - Shutter Delay where:
Row Time Overhead Time
Shutter Delay
= (Reg0x04 + HBLANK_REG) x PIXCLK_PERIOD master clock periods = 64 master clock periods = Reg0x0C x PIXCLK_PERIOD master clock periods In this expression, the row time term, Reg0x09 x row time, corresponds to the number of rows integrated. The overhead time (64 master clocks) is the overhead time between the READ cycle and the RESET cycle, and the final term is the effect of the shutter delay. Typically, the value of Reg0x09 is limited to the number of rows per frame (which includes vertical blanking rows), such that the frame rate is not affected by the integration time. If Reg0x09 is increased beyond the total number of rows per frame, MT9M011 will add additional blanking rows as needed. A second constraint is that tINT must be adjusted to avoid banding in the image from light flicker. Under 60Hz flicker, this means t INT must be a multiple of 1/120 of a second. Under 50Hz flicker, tINT must be a multiple of 1/100 of a second.
Maximum Shutter Delay
The maximum shutter delay is set by the reset cycle time and the overall row time available. It will differ for 1 and 2 ADC mode, as shown in the equations below: 2 ADC Mode: max_shutter_delay = row time - 385 = row time - (365 + 20 x (Reg0x22, bit 8)) = row time - (sampling time + resetting time + dark cols + overhead) 1 ADC Mode: max_shutter_delay = row time - 614 = row time - (574 + 2 x 20 (Reg0x22, bit 8))
Flash Description
Reg0x23 The MT9M011 supports both Xenon and LED flash through the FLASH_STROBE output pin. The timing of the FLASH_STROBE pin with the default settings are shown in Figure 19, Figure 20, and Figure 21. Additionally, the flash can be programmed to only be fired once, be delayed by a few frames when asserted, or programmed for other timing, as described in Table 7 on page 19. Since enabling the LED flash will cause one bad frame, where several of the rows only had the flash on for part of their integration time, it is recommended to do a restart (Reg0x0D, bit 1) of the sensor when enabling the flash. The first bad frame will then be masked out as shown in Figure 21.
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Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Feature Description Figure 19: Xenon Flash Enabled
FRAME_VALID
FLASH_STROBE
Figure 20: LED Flash Enabled (integration time = number of rows in a frame)
FRAME_VALID
Bad frame
FLASH_STROBE Flash enabled during this frame Bad frame Good frame Good frame Flash disabled during this frame
Figure 21: LED Flash Enabled with Restart (integration time = number of rows in a frame)
FRAME_VALID Masked out frame Masked out frame Good frame Good frame Flash disabled and a restart triggered
FLASH_STROBE Flash enabled and a restart triggered
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Feature Description
Recommended Gain Settings The gains for green1, blue, red, and green2 pixels are set by registers Reg0x2B, Reg0x2C, Reg0x2D, and Reg0x2D, respectively. Gain can also be set globally by Reg0x2F. The analog gain is set by bits[8:0] of the corresponding register as following: Gain = (Bit[8] + 1) x (Bit[7] + 1) x (Bit[6:0]/32) Digital gain is set by bits 9 and 10 of the same registers. The analog gain circuitry (pre-ADC) is designed to offer signal gains from 1 to 15.875. The minimum gain of 1 (register set to 0x0020) corresponds to the lowest setting where the pixel signal is guaranteed to saturate the ADC under all specified operating conditions. Any reduction of the gain below this value may cause the sensor to saturate at ADC output values less than the maximum, under certain conditions. It is recommended that this guideline be followed at all times. Since bits 7 and 8 of the gain registers are multiplicative factors for the gain settings, there are alternative ways of achieving certain gains. Some settings offer superior noise performance to others, while the same overall gain. Table 8 lists the recommended gain settings.
Table 8:
Recommended Gain Settings
Desired Gain 1.000 to 1.969 2.000 to 7.938 8.000 to 15.875 Recommended Settings (gain registers) 0x020 to 0x03F 0x0A0 to 0x0FF 0x1C0 to 0x1FF Conversion Formula (arithmetic) (Register value)/32 (Register value - 128)/16 (Register value - 384)/8
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Electrical Specifications
Electrical Specifications
Table 9: DC Electrical Characteristics
(VDD = VAA = VDDQ = 2.8V; TA = 25C; 13.9 fps at 25 MHz) Symbol VIH VIL IIN VOH VOL IOZ IPWR Definition Input High Voltage Input Low Voltage Input Leakage Current Output High Voltage Output Low Voltage Tri-state Output Leakage Current Total Quiescent Supply Current2 Total Standby Supply Current2 Conditions MIN VDD - 0.3 -0.3 -15 VDDQ 0 0.2 15 CLKIN = 25 MHz; default settings; CLOAD = 68.5pF STANDBY = VDDQ1, CLKIN = 0 MHz 46 68 TYP MAX VDD + 0.3 0.8 15 Units V V A V V A mA
No Pull-up Resistor; VIN = VDD or DGND
IPWR Standby
1
10
A
Notes: 1. To place the chip in standby mode, first raise STANDBY to HIGH then wait ten master clock cycles before turning off the master clock. Ten master clock cycles are required to place the analog circuitry into standby, low-power mode. 2. Summation of currents for all power supplies.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Electrical Specifications Table 10: AC Electrical Characteristics
TA = Ambient = 25C; Load capacitance = 68.5pF; Master clock frequency = 25 MHz) Symbol FCLK_IN
t t t t t t DUTY_CYCLE CLK_JITTER R
Definition Input Clock Frequency Clock Input Duty Cycle Input Clock Jitter Input Clock Rise Time Input Clock Fall Time CLKIN to PIXCLK propagation delay LOW-to-HIGH HIGH-to-LOW CLKIN to DOUT<:9:0> propagation delay LOW-to-HIGH HIGH-to-LOW Setup time for FRAME_VALID before rising edge of PIXCLK Hold time for FRAME_VALID after falling edge of PIXCLK Setup time for LINE_VALID before rising edge of PIXCLK Hold time for LINE_VALID after falling edge of PIXCLK Setup Time for DOUT before rising edge of PIXCLK Hold Time for DOUT after falling edge of PIXCLK Time between rising edge of FRAME_VALID and LINE_VALID DOUT Rise Time DOUT Fall Time CLKIN to FRAME_VALID propagation delay, LOW-to-HIGH CLKIN to LINE_VALID propagation delay, LOW-to-HIGH CLKIN to FRAME_VALID propagation delay, HIGH-to-LOW CLKIN to LINE_VALID propagation delay, HIGH-to-LOW
MIN 1
TYP 25 50
MAX 25
Units MHz % % ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
F PLHP PHLP
12 13 18 15 7 20 8 25 6 240 12 11 7 7 4 5
tPLHD t
PHLD
tFVSETUP tFVHOLD tLVSETUP tLVHOLD tDSETUP tDHOLD tFTOL tOUTR tOUTF tPLHF tPLHL tPHLF tPHLL
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Electrical Specifications Propagation Delay for FRAME_VALID and LINE_VALID Signals
The LINE_VALID and FRAME_VALID signals change on the same rising master clock edge as the data output. The LINE_VALID goes HIGH on the same rising master clock edge as the output of the first valid pixel's data and returns LOW on the same master clock rising edge as the end of the output of the last valid pixel's data. As shown in the "Output Data Format" on page 8 and "Output Data Timing" on page 9, FRAME_VALID goes HIGH 6 pixel clocks prior to the time that the first LINE_VALID goes HIGH. It returns LOW 6 pixel clocks after the last LINE_VALID goes LOW. Note that the data outputs change on the rising edge of the master clock.
Figure 22: Propagation Delays for FRAME_VALID and LINE_VALID Signals
tPLHF,L tPHLF,L CLKIN
CLKIN
FRAME_VALID LINE_VALID
FRAME_VALID LINE_VALID
Figure 23: Propagation Delays for PIXCLK and Data Out Signals
tR tF
CLKIN
tPLHP tPHLP
PIXCLK
tPLHD, tPHLD
DOUT (9:0)
DOUT (9:0)
DOUT (9:0)
DOUT (9:0)
DOUT (9:0)
Figure 24: Data Output Timing Diagram
tFVSETUP
PIXCLK
tLVSETUP tDSETUP tDHOLD tLVHOLD tFTOL tFVHOLD
FRAME_VALID
LINE_VALID DOUT
tOUTR tOUTF
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Electrical Specifications Two-wire Serial Bus Timing
The two-wire serial bus operation requires certain minimum master clock cycles between transitions. These are specified in the following diagrams in master clock cycles.
Figure 25: Serial Host Interface Start Condition Timing
5 SCLK 4
SDATA
Figure 26: Serial Host Interface Stop Condition Timing
5 SCLK 4
SDATA
Note:
All timing are in units of master clock cycle.
Figure 27: Serial Host Interface Data Timing for Write
4 SCLK 4
SDATA
Note:
SDATA is driven by an off-chip transmitter.
Figure 28: Serial Host Interface Data Timing for Read
5 SCLK
SDATA
Note:
SDATA is pulled LOW by the sensor, or allowed to be pulled HIGH by a pull-up resistor offchip.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Electrical Specifications Figure 29: Acknowledge Signal Timing After an 8-Bit Write to the Sensor
6 SCLK Sensor pulls down SDATA pin 3
SDATA
Figure 30: Acknowledge Signal Timing After an 8-Bit Read from the Sensor
7 SCLK Sensor tri-states SDATA pin (turns off pull down) 6
SDATA
Note:
After a read, the master receiver must pull down SDATA to acknowledge receipt of data bits. When read sequence is complete, the master must generate a no acknowledge by leaving SDATA to float HIGH. On the following cycle, a start or stop bit may be used.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Electrical Specifications Spectral Response Figure 31: Spectral Response
Relative Spectral Response
1.4 1.2 1.0
G B R
Relative Response
0.8 0.6 0.4 0.2 0.0
350 450 550 650 750 850 950 1050
Wavelength (nm)
(R)
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. Preliminary: This data sheet contains initial characterization limits that are subject to change upon full characterization of production devices.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
Preliminary
MT9M011 - 1/3-Inch Megapixel Image Sensor Revision History
Revision History
* Rev. D, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1/05 * Changed master clock frequency to 25 MHz in Table 1, and updated related timings in Table 3 * Added settings for maximum frame rate and updated description to Table 7, Register Description, on page 19--Reg0x05 and Reg0x07 * Changed current values and conditions in Table 9, DC Electrical Characteristics, on page 35 * Updated Table 10, AC Electrical Characteristics, on page 36 * Removed ICSP package information and ball description * Rev. C, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8/04 * Updated Table 5, Register List and Default Value, on page 16 * Updated Table 7, Register Description, on page 19 * Rev. B, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7/04 * Updated Table 1, Key Performance Parameters, on page 1 * Updated Figure 2 on page 5 * Replaced Ballout drawing * Updated Table 5, Register List and Default Value, on page 16 * Updated "Electrical Specifications" on page 35 * Rev. A, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preliminary3/04 * Original release
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.

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